The non-volatile storage having flash memory that is one of non-volatile memories reads and writes data by translating a logical address given in order to access flash memory to a physical address. Then, it has address management information for this address translation.
As a background art of this technical field, there is Japanese Unexamined Patent Application Publication No. 2004-199605 (Patent Document 1). Japanese Unexamined Patent Application Publication No. 2004-199605 describes the following: the address management information of the non-volatile memory is stored in non-volatile memory, and only a necessary part of the address management information is read into volatile memory and used; and when updating an AT (address administration table) that occurs at a time of data update, the next AT is written in a writing area different from that of the current AT.
Moreover, there is Japanese Unexamined Patent Application Publication No. 2002-73409 (Patent Document 2). Japanese Unexamined Patent Application Publication No. 2002-73409 describes the following: part of an address translation table is held in the RAM; and when the address translation information corresponding to a logical address does not exist in the RAM, the part of the address translation table in the RAM is copied to non-volatile memory, and the part of the address translation table corresponding to the logical address in the non-volatile memory is copied.
Moreover, there is Japanese unexamined patent application publication No. 2004-127185 (Patent Document 3). Japanese unexamined patent application publication No. 2004-127185 described the following: a memory card has non-volatile memory capable of being erased and written, e.g., flash memory, buffer memory including DRAM, SRAM, or the like, a card controller for controlling memories and controlling an external interface on a mounting substrate; and the flash memory has an erase table and an address translation table in a part of its memory array. Furthermore, it describes that a storage area (a memory array) of the flash memory is roughly divided into the erase table, the address translation table, a user area, and a free block area that becomes necessary when updating the erase table and the address translation table.
Furthermore, there is U.S. Pat. No. 5,900,016 (Patent Document 4). U.S. Pat. No. 5,900,016 describes a cache control logic using a dirty bit regarding a computer system that contains a microprocessor, cache memory, and main memory.
Moreover, there is 2011 Symposium on VLSI Technology, Digest of Technical Papers, pp. 96-97. 2011 Symposium on VLSI Technology, Digest of Technical Papers, pp. 96-97 describes a semiconductor memory device that has pieces of phase change memory stacked on top of one another. Moreover, it describes that the semiconductor memory device is of a large capacity and can be accessed at high speed.